Forum Discussion
New ContributorAgilex 5/3 FreeRTOS SMP Support
New MemberHi sonycman,
The qspi_image.jic contains the properties of the .sof file we used to build the application. The sof file decides where the HPS or FPGA gets configured first. So it can't support both modes at once.
In FPGA first boot, the bitstream gets configured at boot automatically. For the HPS first boot, the FPGA doesn't get configured until we use the fpga_manager driver to configure the FPGA. To make this easier, the sd_img contains the core.rbf bitstream file required for FPGA configuration so that the user doesn't need to build it and copy it.
Hope this helps
New ContributorHi kevinsuresh,
Thank you, now i get it. There is much to learn for me :)
It seems bl31 secure monitor could not be excluded entirely? Its services heavily used?
- kevinsuresh
Hi sonycman,
Glad I could help earlier.The secure monitor is used by the FPGA configuration module and the SDM mailbox module. The Remote System Update(RSU) library, FPGA cryptographic services library and the SEU module rely on the mailbox which in turn invoke the BL31 services through the Secure Monitor Call.
The FPGA related modules like the FPGA manager and bridge modules directly use the Secure Monitor Call for performing FPGA related functions. Some modules like USB3.1 require the FPGA to be configured for it to work successfully.
If the sof file can be a FPGA first boot, and the SDM mailbox dependant modules are not required, we can avoid using SMC calls.
- sonycman
Hi kevinsuresh,
The AI tells me that booting secondary CPU cores also done with the bl31 help. Not sure if its true.
- kevinsuresh
Hi sonycman,
That had slipped my mind. You're right, the secure monitor call is used for bringing up the secondary cores.
