wire assignment in verilog

No. Z (high impedance) or X (don't care) are not valid logic levels internal to the hardware of the FPGA. So anything not defined has to go to 0. They could be X in a simulation depending on your design if that's what you mean.

Quartus provides warning messages when vector sizes don't match like this.

This is back to Verilog IEEE Standard 1364-2005 (Section 5.1.14) specifies this zero-extension behavior. While QuestaSim adheres to this standard, specific QuestaSim documentation may not explicitly restate this behavior, as it is a fundamental aspect of the Verilog language itself.

If you really want to use it, you will need to write like the below:

assign A = {8'bx, {8{B}}}; // Fills the upper 8 bits with 'x'

The warning message for the bit size does not appear in the Questa Compiler. Is there a way to check if there is a code error for an unallocated bit like the above?

I dont think so, you will need to run the simulation waveform to notice this.

Could you look at the two pictures? The signal D defined as 44 bits was divided into 16 bits/16 bits/12 bits and allocated 8 bits each. And as a result of running the simulation, the value of 0 was automatically assigned for the undefined upper bits, and when the value of 1 was given, only the defined 8 bits responded to the value. There was no warning message during the compile process.

input A;

input B;

input C;

output [43:0] D;

assign D[15: 0] = {8{A}};
assign D[31:16] = {8{B}};
assign D[43:32] = {8{C}};

I wrote the code like this.

So what does your testbench look like?

Can you attached your testbench as well, but I think the explanation cannot run far away from my previous comment.

Is there any update for this?

Sorry for the late response. The test bench I made is simply defining those signals and signaling and turning them off one by one over time. I've posted on several forums, but all the answers are 'automatically allocating zero for the remaining bits' in the code I put together. This has been resolved. The only question is whether Modelsim or Questa doesn't warn you about the bit allocation mismatch. Are there any settings that allow Modelsim or Questa to notice warning messages about the bit allocation width?