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junyoung2
New Contributor
New Contributorwire assignment in verilog
Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of s...
junyoung2New Contributor
New ContributorSorry for the late response. The test bench I made is simply defining those signals and signaling and turning them off one by one over time. I've posted on several forums, but all the answers are 'automatically allocating zero for the remaining bits' in the code I put together. This has been resolved. The only question is whether Modelsim or Questa doesn't warn you about the bit allocation mismatch. Are there any settings that allow Modelsim or Questa to notice warning messages about the bit allocation width?
