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junyoung2
New Contributor
New Contributorwire assignment in verilog
Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of s...
junyoung2New Contributor
New Contributorinput A;
input B;
input C;
output [43:0] D;
assign D[15: 0] = {8{A}};
assign D[31:16] = {8{B}};
assign D[43:32] = {8{C}};
I wrote the code like this.
