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junyoung2
New Contributor
New Contributorwire assignment in verilog
Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of s...
sstrell
Super Contributor
Super ContributorNo. Z (high impedance) or X (don't care) are not valid logic levels internal to the hardware of the FPGA. So anything not defined has to go to 0. They could be X in a simulation depending on your design if that's what you mean.
Quartus provides warning messages when vector sizes don't match like this.
- junyoung2
I found this problem when I was using Questasim from intel. Does Questa define it as a value of zero for unallocated bits? Is there a document to refer to in this regard?
