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junyoung2
New Contributor
New Contributorwire assignment in verilog
Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of s...
KennyT_altera
Super Contributor
Super ContributorThis is back to Verilog IEEE Standard 1364-2005 (Section 5.1.14) specifies this zero-extension behavior. While QuestaSim adheres to this standard, specific QuestaSim documentation may not explicitly restate this behavior, as it is a fundamental aspect of the Verilog language itself.
If you really want to use it, you will need to write like the below:
assign A = {8'bx, {8{B}}}; // Fills the upper 8 bits with 'x'
