Forum Discussion
junyoung2
New Contributor
New Contributorwire assignment in verilog
Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of s...
junyoung2New Contributor
New ContributorCould you look at the two pictures? The signal D defined as 44 bits was divided into 16 bits/16 bits/12 bits and allocated 8 bits each. And as a result of running the simulation, the value of 0 was automatically assigned for the undefined upper bits, and when the value of 1 was given, only the defined 8 bits responded to the value. There was no warning message during the compile process.
- sstrell
Super Contributor
Can you show the actual code?
