Why is my inout signal converted to output by eda netlist writer?

My simple test dut consists of the following code. When I run a compile on this code (Processing ->start Compilation) the netlist written by the EDA Netlist Writer has signal defined as output instead of inout. I am unable to figure out what I am doing wrong. Any hints or help in identifying the issue is welcome.

module test(                                                    
        input dir,
        inout signal,        
        input clk,
        input rst_n
);                                              
reg intreg;
always @(posedge clk or negedge rst_n)begin
        if (~rst_n)
                intreg<=1'b0;                                         
        else begin
                if (dir)
                        intreg<=signal;
        end  
end         
assign signal=dir?1'bz:intreg;
endmodule   

// Device: Altera 10M08SCE144C8G Package EQFP144
//
//
// This Verilog file should be used for ModelSim-Altera (Verilog) only
//                                              
`timescale 1 ps/ 1 ps
        
module test (   
        dir, 
        signal,
        clk,            
        rst_n);
input   dir; 
output  signal;
input   clk;
input   rst_n;