Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorWhy is my inout signal converted to output by eda netlist writer?
My simple test dut consists of the following code. When I run a compile on this code (Processing ->start Compilation) the netlist written by the EDA Netlist Writer has signal defined as output inste...
Altera_ForumHonored Contributor
Honored ContributorI guess it was an issue with the Linux versions of the tool. Didn't see this in the windows versions.
