Why is my inout signal converted to output by eda netlist writer?

The zip file was created using tool version 17.0, I will recheck with 17.1

In case it matters, my system is

%uname -a

Linux Dyumnin 4.13.0-16-generic# 19-Ubuntu SMP Wed Oct 11 18:35:14 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux

For the Altera example code, I did not change any settings.

My Process was as follows.

mkdir output

cp bidirec.v output

cd output

{Launch Quartus}

{Do File->New->New Quartus Prime Project}

{select the device, project folder and verilog file}

{Do Processing->StartCompilation}

{Check netlist writer has generated inout port: YES}

{Do Processing->StartCompilation}

{Check netlist writer has generated inout port: NO}