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Altera_Forum
Honored Contributor
Honored ContributorWhy is my inout signal converted to output by eda netlist writer?
My simple test dut consists of the following code. When I run a compile on this code (Processing ->start Compilation) the netlist written by the EDA Netlist Writer has signal defined as output inste...
Altera_ForumHonored Contributor
Honored ContributorHave you checked your design with the RTL Viewers and Netlist viewers? This will give you an idea how the logic/pin was implemented in the FPGA.
