Why is my inout signal converted to output by eda netlist writer?

--- Quote Start ---

Have you checked your design with the RTL Viewers and Netlist viewers? This will give you an idea how the logic/pin was implemented in the FPGA.

--- Quote End ---

I tried compiling Altera's bidirectional port example I find that the results are not consistent, The first compile results in a netlist with an inout port, the second compile results in a netlist with an output port.

All I had to do is click Processing->StartCompilation twice to get these two results

https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_bidirec.html