Why is my inout signal converted to output by eda netlist writer?

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I tried compiling Altera's bidirectional port example I find that the results are not consistent, The first compile results in a netlist with an inout port, the second compile results in a netlist with an output port.

All I had to do is click Processing->StartCompilation twice to get these two results

https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_bidirec.html

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I have attached the two netlists generated using the above process.

Observe the content of the /simulation/modelsim/bidirec.vo

grep -a2 "^output" */simulation/modelsim/bidirec.vo

inout/simulation/modelsim/bidirec.vo-input clk;

inout/simulation/modelsim/bidirec.vo-input [7:0] inp;

inout/simulation/modelsim/bidirec.vo:output [7:0] outp;

inout/simulation/modelsim/bidirec.vo-inout [7:0] bidir;

inout/simulation/modelsim/bidirec.vo-

--

output/simulation/modelsim/bidirec.vo-input clk;

output/simulation/modelsim/bidirec.vo-input [7:0] inp;

output/simulation/modelsim/bidirec.vo:output [7:0] outp;

output/simulation/modelsim/bidirec.vo:output [7:0] bidir;