Forum Discussion
QuartusPro 25.3 Crashed after using the Signal Tap Logic Analyzer
When I execute the Signal Tap Logic Analyzer function on QuartusPro 25.3, after finding and viewing the signal I wanted , then saving it, the crash was happend. I also saved the log by clicking "preview report".
the part of log message as below.
*** Fatal Error: Segment Violation: faulting address=(nil), PC=0x7f9af7f4acff : 0x7f9af7f4acff: sld_sdr!SDR_TX_SIGNAL_NODES_GEN2::get_parent_index(int, int) + 0x29
Module: quartus
Stack Trace:
Err Handler 0x327e1: ERR_UNWINDER_BACKTRACE::get_stack_trace(void const**, int, int, void*) + 0xed (ccl_err)
Err Handler 0x8f7b0: msg_ie_get_call_stack(void*) + 0xc4 (ccl_msg)
Err Handler 0x91b16: MSG_INTERNAL_ERROR::report_fatal(char const*, void*, bool) + 0x40 (ccl_msg)
Err Handler 0x123c7: err_report_fatal_exception(char const*, void*, bool) + 0x63 (ccl_err)
Err Handler 0x24f40: err_sigaction_handler + 0x727 (ccl_err)
System 0xf630: (pthread)
2 Replies
- sstrell
Super Contributor
First, have you applied the patch: Intermittent DDM Errors | Altera Community - 349752
Is the crash consistent/repeatable?
- RichardT_altera
Super Contributor
As mentioned by sstrell, could you please clarify whether the crash is intermittent or repeatable?
Additionally, please check whether the crash still occurs after applying the patch from the KDB.
https://community.altera.com/kb/knowledge-base/why-do-i-unexpectedly-observe-intermittent-ddm-errors/349714
If the issue persists, kindly provide the design .QAR file (Project → Archive Project) so that I can attempt to reproduce the issue.
Regards,
Richard Tan