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Altera_Forum's avatar
Altera_Forum
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8 years ago

Why is my inout signal converted to output by eda netlist writer?

My simple test dut consists of the following code. When I run a compile on this code (Processing ->start Compilation) the netlist written by the EDA Netlist Writer has signal defined as output inste...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I just tried re-compiling both your code as well as the Altera example, and both times, I get the same logic inferred - Bidir IO . If you're getting inconsistent results, check the tool settings if you have modified any and revert back to Defaults.

I'm also using the latest QPrime 17.1. This should not happen irrespective of the tool version and number of times the same design is being compiled. The only way this can happen is if there's been some setting changed in the tool or some other constraints modified.