New ContributorStrange issues on FPGA
Hi All,
I wrote a simple finite state machine Verilog code and ran it on the FPGA, but it never runs stably.
My environment:
- MAX10 10m08 EVB
- Quartus Prime Lite 23.1.1
My Verilog Code:
module top ( input wire clk, // Clock signal input wire rst, // Reset signal // input wire enable_1, // input wire enable_2, input wire DIO_Tick, output reg Tick_FPGA_1, // output reg Tick_FPGA_2, // input wire rx_1, // input wire rx_2, input wire data_valid, input wire [11:0] data_in, output reg [11:0] data_out, // output wire gpio_1, // output wire gpio_2, output reg led_1, led_2, led_3, led_4 ); reg [2:0] state; reg [3:0] counter; parameter IDLE = 3'b000; parameter START = 3'b001; parameter WAIT = 3'b010; parameter BUSY_1 = 3'b011; always @(posedge clk or negedge rst) begin if(!rst) begin Tick_FPGA_1 <= 1; // Tick_FPGA_2 <= 1; state <= IDLE; end else begin case(state) IDLE: begin led_1 <= 0; led_2 <= 1; led_3 <= 1; led_4 <= 1; if(!DIO_Tick) begin state <= START; end end START: begin Tick_FPGA_1 <= 0; // counter <= counter + 4'h1; led_1 <= 1; led_2 <= 0; led_3 <= 1; // if(counter == 4'h4) begin // counter <= 0; state <= WAIT; // end end WAIT: begin state <= BUSY_1; end BUSY_1: begin led_1 <= 1; led_2 <= 1; led_3 <= 0; Tick_FPGA_1 <= 1; if(!data_valid) begin data_out <= data_in; state <= IDLE; end end endcase end end endmodule
It encounters two issues:
1. Tick_FPGA cannot return to a high level; based on the LED status, it does not correctly transition to the BUSY_1 state.
2. It does not correctly receive data_valid, causing it to get stuck in the BUSY_1 state and unable to return to the IDLE state.
I've tested many methods, such as:
For Issue 1, I originally used a counter to maintain Tick_FPGA = 0 for a while before transitioning states, but I changed it to not use a counter.
For Issue 2, I extended the duration of data_valid, switched to edge detection, and implemented debouncing to wait for stability, but it still cannot run stably.
I'm out of options and need your help.
