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Re: Quartus error libpng12.so.0 on Ubuntu 22.04
Thanks for the reply! Yeah I also noticed that I was lucky with 20.04, as I install Quartus 17.1 on a Ubuntu 20.04 VM, got the same error as above. I am already using a newer version of Quartus for the project, a year ago or sth I upgraded the project from Quartus 17.1 to 21.3 Pro, but recently we're experiencing some differences at the output data (the VHDL code and the IP parameters weren't changed, only the Quartus upgrade). That's why I wanted to re-synthesize the project on 17 and 21.3 to check the IP cores if possible.244Views0likes0CommentsQuartus error libpng12.so.0 on Ubuntu 22.04
Hi all, I'm trying to run Quartus Prime 17.1 Standard version on my Ubuntu 22.04 system. I recently upgraded my pc to Ubuntu 22 from Ubuntu 20.04, and back then I could run Quartus 17.1 without any issues. Now when I try to run it on Ubuntu 22, I'm getting this error message: quartus: error while loading shared libraries: libpng12.so.0: cannot open shared object file: No such file or directory I've tried installing libpng12 to my computer but it didn't help. Followed all the tips I could find online but I still cannot launch Quartus 17 on my pc. Has any of you guys experienced the same (or similar) issue here and managed to solve it ? Cheers520Views0likes3CommentsRe: 10CX085YF672E6Gga
Hi, I do see that the two letter part you're referring to is called 'Optional Suffix', but there are no further details about it in the datasheet that simply lists all optional suffix options for more clarity. But imo it shouldn't affect its functionality Cheers440Views0likes0CommentsRe: No Nios II target connection
Hi, I'm having the same issue with my Cyclone 10 FPGA on Ubuntu 20.04 and tried everything @AnandRaj_S_Intel suggested. I also tried running the nios2_command_shell script and then ran 'nios2-terminal', which couldn't run due to the lack of detected devices. But when I run jtagconfig, I can see my blaster connected and also the Cyclone under it, just like the snippet above. Cheers510Views0likes1CommentRe: Publication of the FPGA bitstream (.pof) as Open Source
I definitely understand your concern. However, unless you have an exclusive support from Intel, posting on the community and waiting for their reply is the way to go unfortunately. And yes, they can be extremely slow at replying to your question. So if there’sa tight urgency, you might consider getting the exclusive support (which I assume is very expensive)1.8KViews0likes1CommentRe: Publication of the FPGA bitstream (.pof) as Open Source
Hi, I have no experience on this, but sharing the binary should be fine, because you cannot get the source code or project from the binary. But I have to say that binaries are generated depending on the content of your project AND the target Fpga board. So not everyone that you share the .pof with can make use of the binary unless they have the exact same part themselves. This means, either both parties must have the same FPGA part, or you have to generate binaries for the same project with different Fpga parts 🙂1.8KViews0likes3CommentsRe: arria 10 lvds serdes
Hi, I have done it, and it seems like the errors I got are related to the connection of 'rx_dpa_locked'. But feels odd because the compiler complains about the rx_out's connection whereas the errors are gone when I make the dpa_locked connection of the exported qsys component open.638Views0likes0Comments