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Scarlet's avatar
Scarlet
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2 years ago

Strange issues on FPGA

Hi All, I wrote a simple finite state machine Verilog code and ran it on the FPGA, but it never runs stably. My environment: - MAX10 10m08 EVB - Quartus Prime Lite 23.1.1 My Verilog Code: ...
Compilation
Hdl
anonimcs's avatar
anonimcs
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2 years ago

Hi,

Firstly, could you add the snippets a bit close-up ? It's really hard to see the details, therefore to debug. Regarding the issues:

1) If the Tick_FPGA is staying low, your FSM might be stuck at the IDLE state, waiting for Dio_tick. In the second snippet I see that there's a rapid transition of Dio_tick to 0 and then back to 1, maybe this transition happens when the FSM is not in the IDLE state but in another state. But since there's no state signal in the waveforms, I cannot be sure. Maybe you can add that one and the counter signals to the waveform ?

2) What is DATA in A4 ? data_in or data_out ? If it's data_in, it could be the same as 1), getting the data_valid transition to 0 in another state. But if it's data_out, it should be stuck in the BUSY_1 state indeed, but that shouldn't be the case given that the data_valid is wide enough for the clock to catch.

My idea is that you're stuck at the reset state for the most of the time, and when it's out of that, the FSM barely has time to do anything (I assume A4 is data_in)

FvM's avatar
FvM
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2 years ago
I agree with above post that shown timing recordings don't give much information to debug the issue, except for the simple fact that the state machine is stuck.

That's not strange but a well-known effect of state machines reading asynchronous input signals without necessary synchronizer chain. If the input changes simultaneous with clock edge, the FSM can jump to an illegal state and possibly never leave it.
  • Scarlet's avatar
    Scarlet
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    2 years ago
    @FvM wrote:
    I agree with above post that shown timing recordings don't give much information to debug the issue, except for the simple fact that the state machine is stuck.

    I've added additional explanations in the previous response.

    @FvM wrote:
    That's not strange but a well-known effect of state machines reading asynchronous input signals without necessary synchronizer chain. If the input changes simultaneous with clock edge, the FSM can jump to an illegal state and possibly never leave it.

    Yes, I learned after working with FPGA that if the input changes simultaneously with the clock edge, it can cause errors. That's why I tried adding synchronization to wait for the external signal to stabilize, but it seems to not resolve the issue of not receiving the external data_valid signal.

    		data_valid_sync1 <= data_valid;
		data_valid_sync2 <= data_valid_sync1;