Documentation of recent low-level and WYSIWYG primitives

Hello,
it has been previously stated that Altera doesn't provide documentation of low-level primitives for newer FPGA series, e.g. Cyclone 10 GX or Agilex. See e.g. WYSIWYG documentation | Altera Community - 273853

What if I want to implement e.g. an octal SPI interface utilizing DDR and DQS driven data sampling with calibration? I presume that my IP would use tennm_io_12_lane and tennm_tile_ctrl primitives. They are published in Quartus as interface definition in tennm_components and a .xml parameter list.

Can you provide additional information under NDA?

Regards
Frank