Strange issues on FPGA

Hi Scarlet,
it's quite simple, any signal originated outside the FSM clock domain and used to advance state must be synchronized to FSM clock.

@anonimcs wrote

It's always good to add a default state to prevent (and more importantly recover from) these as much as possible.

Unfortunately, a default state will not help to recover from illegal states. If there's no condition advancing to a certain state, it will be simply discarded in synthesis.

To achieve this, you need to specify safe state machine encoding by synthesis attribute

type state_type is (s0, s1, s2, s3);
signal state : state_type := s0;
attribute syn_encoding : string;
attribute syn_encoding of state_type : type is "safe";

Review "State Machine HDL Guidelines" in Quartus Design Manual for details.