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Honored Contributor
Honored ContributorSetting up SDC for input I/O?
Hi,
I'm having I/O setup violations on input pins. The clock is driven by the FPGA, goes to an external FIFO that clocks out data to the FPGA inputs. The Tco of the external FIFO is max 7.7ns, min 4.1ns. I'm getting some 100+ slow model setup violations on the input side. This is the SDC i'm using: # ************************************************************** # Time Information # ************************************************************** set_time_format -unit ns -decimal_places 3 # ************************************************************** # Create Clock # ************************************************************** create_clock -name CLK_IN_48 -period 20.833 -waveform { 0.000 10.416 } [get_ports CLK_IN_48] # ************************************************************** # Create Generated Clock # ************************************************************** create_generated_clock -name pll_clk_60 -source [get_pins inst|altpll_component|pll|inclk[0]] -duty_cycle 50.000 -multiply_by 5 -divide_by 4 -master_clock CLK_IN_48 [get_pins inst|altpll_component|pll|clk[1]] -add create_generated_clock -name CLK_OUT_60 -source [get_pins inst|altpll_component|pll|clk[1]] [get_ports CLK_OUT_60] # ************************************************************** # Set Input Delay # ************************************************************** set_input_delay -max -clock [get_clocks CLK_OUT_60] 7.7 [get_ports LINKDATA[*]] set_input_delay -min -clock [get_clocks CLK_OUT_60] 4.1 [get_ports LINKDATA[*]] When looking at the top failing path (tsu) in the chip planner i see that 7.7ns has been added as iExt input delay per my above SDC. The total path delay is some 1.6ns too large. Is it correct to use the CLK_OUT_60 node as clock reference in the SDC or should i use the 'pll_clk_60' name in the set_input_delay SDC statement? The latter works but i'm suspecting the the former is correct. This is the path report (report_timing -to_clock {pll_clk_60} -setup -npaths 1 -detail path_only) Info: Path# 1: Setup slack is -1.593 (VIOLATED) Info: =================================================================== Info: From Node : LINKDATA[5] Info: To Node : MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a31~portb_we_reg Info: Launch Clock : CLK_OUT_60 Info: Latch Clock : pll_clk_60 Info: Info: Data Arrival Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 0.000 0.000 launch edge time Info: 2.939 2.939 R clock network delay Info: 10.639 7.700 F iExt LINKDATA[5] Info: 11.563 0.924 FF CELL LINKDATA[5]|combout Info: 13.295 1.732 FF IC inst5|OUTDATA[5]~638|datac Info: 13.617 0.322 FF CELL inst5|OUTDATA[5]~638|combout Info: 13.923 0.306 FF IC inst7|out_msg_data_valid~161_RESYN620|datad Info: 14.101 0.178 FF CELL inst7|out_msg_data_valid~161_RESYN620|combout Info: 14.394 0.293 FF IC inst7|out_msg_data_valid~161|datad Info: 14.572 0.178 FF CELL inst7|out_msg_data_valid~161|combout Info: 14.882 0.310 FF IC inst2|inst11|HEADER[6]~106SynDup|datac Info: 15.204 0.322 FR CELL inst2|inst11|HEADER[6]~106SynDup|combout Info: 15.525 0.321 RR IC inst2|inst2|scfifo_component|auto_generated|dpfifo|fifo_state|valid_wreq~SynDup_1|datad Info: 15.703 0.178 RR CELL inst2|inst2|scfifo_component|auto_generated|dpfifo|fifo_state|valid_wreq~SynDup_1|combout Info: 17.717 2.014 RR IC inst2|inst2|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram2|altsyncram3|ram_block4a31|ena1 Info: 18.459 0.742 RR CELL MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a31~portb_we_reg Info: Info: Data Required Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 16.666 16.666 latch edge time Info: 16.906 0.240 R clock network delay Info: 16.866 -0.040 uTsu MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a31~portb_we_reg Info: Info: Data Arrival Time : 18.459 Info: Data Required Time : 16.866 Info: Slack : -1.593 (VIOLATED) Info: =================================================================== Info: 1) Is it correct to have a 7.7ns delay inserted in the path? What can be done to lower the path delay? 2) Why has a 2.939 clock network delay been inserted in the path? I would assume that the reference clock is measured on the output package pin CLK_OUT_60 so no additional delay should apply? 3) In fact, since the clock is DRIVEN by the PLL which is (apparently) 2.939ns ahead of the signal on the clock output pin, i would expect to see a -2.939ns improvement in timing if i the -clock in the SDC was set to the PLL output instead of the output clock pin. Is this correct reasoning? Thanks, /John.
