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Altera_Forum
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17 years ago

Setting up SDC for input I/O?

Hi, I'm having I/O setup violations on input pins. The clock is driven by the FPGA, goes to an external FIFO that clocks out data to the FPGA inputs. The Tco of the external FIFO is max 7.7ns, ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Thanks Jake. I'm assuming zero board delay because i have less than an inch of traces.

How can i get rid of the following large clock network delay on the pin output?

Info: 2.939 2.939 R clock network delay

Basically, all timing issues would go away if this could be lowered. Enabling fast I/O or something similar for the clock pin?

Thanks,

/John.