Honored Contributor
Honored ContributorFYI: The timing violation has been worked around by pipelining my design. The problem signal was sent downstream to other modules (inst, inst2, inst5) via combinational logic. By simply registering the output from the first module all timing violations went away. This is the new timing report for the previously failing path:
Info: Path# 1: Setup slack is 1.787 Info: =================================================================== Info: From Node : NXT Info: To Node : LinkState:inst1|curstate[1]_OTERM349 Info: Launch Clock : CLK_OUT_60 Info: Latch Clock : pll_clk_60 Info: Info: Data Arrival Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 0.000 0.000 launch edge time Info: 2.939 2.939 R clock network delay Info: 10.239 7.300 R iExt NXT Info: 11.173 0.934 RR CELL NXT|combout Info: 12.648 1.475 RR IC inst1|RxActiveDetector|Selector1~101|dataa Info: 13.105 0.457 RF CELL inst1|RxActiveDetector|Selector1~101|combout Info: 13.930 0.825 FF IC inst1|Mux6~1761|datad Info: 14.108 0.178 FR CELL inst1|Mux6~1761|combout Info: 14.406 0.298 RR IC inst1|Mux5~2021|datab Info: 14.927 0.521 RR CELL inst1|Mux5~2021|combout Info: 14.927 0.000 RR IC inst1|curstate[1]_NEW_REG348|datain Info: 15.023 0.096 RR CELL LinkState:inst1|curstate[1]_OTERM349 Info: Info: Data Required Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 16.666 16.666 latch edge time Info: 16.772 0.106 R clock network delay Info: 16.810 0.038 uTsu LinkState:inst1|curstate[1]_OTERM349 Info: Info: Data Arrival Time : 15.023 Info: Data Required Time : 16.810 Info: Slack : 1.787 Info: =================================================================== Info:
