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That clock network delay probably isn't what you think it is. Use "-detail full_path" instead of "-detail path_only" for report_timing to see what is in the clock path.
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Thanks. This is the result (new signal top violation since the previous went away via HDL recoding):
Info: Path# 1: Setup slack is -0.905 (VIOLATED)
Info: ===================================================================
Info: From Node : NXT
Info: To Node : MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a5~portb_we_reg
Info: Launch Clock : CLK_OUT_60
Info: Latch Clock : pll_clk_60
Info:
Info: Data Arrival Path:
Info:
Info: Total (ns) Incr (ns) Type Element
Info: ========== ========= == ==== ===================================
Info: 0.000 0.000 launch edge time
Info: 0.000 0.000 source latency
Info: 0.000 0.000 CLK_IN_48
Info: 1.066 1.066 RR CELL CLK_IN_48|combout
Info: 3.525 2.459 RR IC inst|altpll_component|pll|inclk[0]
Info: -2.031 -5.556 RR COMP inst|altpll_component|pll|clk[1]
Info: -1.260 0.771 RR IC inst|altpll_component|_clk1~clkctrl|inclk[0]
Info: -1.260 0.000 RR CELL inst|altpll_component|_clk1~clkctrl|outclk
Info: -0.072 1.188 RR IC CLK_OUT_60|datain
Info: 2.939 3.011 RR CELL CLK_OUT_60
Info: 10.239 7.300 R iExt NXT
Info: 11.173 0.934 RR CELL NXT|combout
Info: 12.770 1.597 RR IC inst1|msg_data_type~435|datac
Info: 13.092 0.322 RR CELL inst1|msg_data_type~435|combout
Info: 13.393 0.301 RR IC inst5|out_msg_data_valid~78|datac
Info: 13.671 0.278 RR CELL inst5|out_msg_data_valid~78|combout
Info: 14.161 0.490 RR IC inst2|inst2|scfifo_component|auto_generated|dpfifo|fifo_state|valid_wreq~_Duplicate_RESYN1008|datad
Info: 14.339 0.178 RR CELL inst2|inst2|scfifo_component|auto_generated|dpfifo|fifo_state|valid_wreq~_Duplicate_RESYN1008|combout
Info: 14.810 0.471 RR IC inst2|inst2|scfifo_component|auto_generated|dpfifo|fifo_state|valid_wreq~_Duplicate|datac
Info: 15.132 0.322 RR CELL inst2|inst2|scfifo_component|auto_generated|dpfifo|fifo_state|valid_wreq~_Duplicate|combout
Info: 17.030 1.898 RR IC inst2|inst2|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram2|altsyncram3|ram_block4a5|ena1
Info: 17.772 0.742 RR CELL MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a5~portb_we_reg
Info:
Info: Data Required Path:
Info:
Info: Total (ns) Incr (ns) Type Element
Info: ========== ========= == ==== ===================================
Info: 16.666 16.666 latch edge time
Info: 16.666 0.000 source latency
Info: 16.666 0.000 CLK_IN_48
Info: 17.732 1.066 RR CELL CLK_IN_48|combout
Info: 20.191 2.459 RR IC inst|altpll_component|pll|inclk[0]
Info: 14.635 -5.556 RR COMP inst|altpll_component|pll|clk[1]
Info: 15.406 0.771 RR IC inst|altpll_component|_clk1~clkctrl|inclk[0]
Info: 15.406 0.000 RR CELL inst|altpll_component|_clk1~clkctrl|outclk
Info: 16.124 0.718 RR IC inst2|inst2|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram2|altsyncram3|ram_block4a5|clk1
Info: 16.907 0.783 RR CELL MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a5~portb_we_reg
Info: 16.867 -0.040 uTsu MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a5~portb_we_reg
Info:
Info: Data Arrival Time : 17.772
Info: Data Required Time : 16.867
Info: Slack : -0.905 (VIOLATED)
Info: ===================================================================
Info:
So, I see that the clock *really* goes from the CLK_48_MHZ input pin, through the PLL, out onto the internal global clock network and finally goes out on the CLK_OUT_60 pin to the external FIFO. What i don't understand is why the zero time is not counted from the external CLK_OUT_60 pin which is what i intended to use as clock in the SDC. I must get something conceptually wrong since i would assume t=0 should be the CLK_OUT_60 element. In fact, if i specify the 60 MHz PLL clock as reference the timing violation goes away - i'm however not sure this approach is correct (neighter of the clock options appear correct, really).
As can be seen in the path above, the major delays are really the 'clock network delay' and the 7.3ns delay to compensate for the external device's Tco. If i can get rid of the 'clock delay' i would meet timing...
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