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Altera_Forum
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17 years ago

Setting up SDC for input I/O?

Hi, I'm having I/O setup violations on input pins. The clock is driven by the FPGA, goes to an external FIFO that clocks out data to the FPGA inputs. The Tco of the external FIFO is max 7.7ns, ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

The correct way to specify the -max delay is to use tCOmax + Data delay max - Clock delay min.

The correct way to specify the -min delay is to use tCOmin + Data delay min - Clock delay max.

Where Data delay is the time delay on the data trace as a result of board delays. Similarly Clock delay is the time delay on the clock trace as a result of board delays.

Jake