Honored Contributor
Honored ContributorThanks everyone for the information. I'm unfortunately completely lost what to do now. It seems my design doesn't meet timing although i don't see the tsu/th or fmax being extreme in any way. Any tips what could be optimized or changed to resolve the above setup violation?
Just as a test, i tried to use the reference_pin option: set_input_delay -max -clock [get_clocks pll_clk_60] -reference_pin [get_ports CLK_OUT_60] 7.3 [get_ports NXT] set_input_delay -min -clock [get_clocks pll_clk_60] -reference_pin [get_ports CLK_OUT_60] 3.8 [get_ports NXT] This results in the following identical path (report_timing -to_clock {pll_clk_60} -from [get_ports {NXT}] -setup -npaths 1 -detail path_only): Info: Path# 1: Setup slack is -0.902 (VIOLATED) Info: =================================================================== Info: From Node : NXT Info: To Node : MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a2~portb_we_reg Info: Launch Clock : pll_clk_60 Info: Latch Clock : pll_clk_60 Info: Info: Data Arrival Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 0.000 0.000 launch edge time Info: 2.939 2.939 R clock network delay Info: 10.239 7.300 R iExt NXT Info: 11.173 0.934 RR CELL NXT|combout Info: 12.880 1.707 RR IC inst1|msg_data_type~434_Duplicate|datad Info: 13.057 0.177 RF CELL inst1|msg_data_type~434_Duplicate|combout Info: 13.969 0.912 FF IC inst7|out_msg_data_valid~161|datac Info: 14.291 0.322 FF CELL inst7|out_msg_data_valid~161|combout Info: 14.598 0.307 FF IC inst2|inst2|scfifo_component|auto_generated|dpfifo|fifo_state|valid_wreq~_Duplicate|datab Info: 15.089 0.491 FR CELL inst2|inst2|scfifo_component|auto_generated|dpfifo|fifo_state|valid_wreq~_Duplicate|combout Info: 17.027 1.938 RR IC inst2|inst2|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram2|altsyncram3|ram_block4a2|ena1 Info: 17.769 0.742 RR CELL MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a2~portb_we_reg Info: Info: Data Required Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 16.666 16.666 latch edge time Info: 16.907 0.241 R clock network delay Info: 16.867 -0.040 uTsu MessageEncoder:inst2|MessageEncoderFifo:inst2|scfifo:scfifo_component|scfifo_0e31:auto_generated|a_dpfifo_f531:dpfifo|dpram_m011:FIFOram|altsyncram_s1k1:altsyncram2|altsyncram_qrc1:altsyncram3|ram_block4a2~portb_we_reg Info: Info: Data Arrival Time : 17.769 Info: Data Required Time : 16.867 Info: Slack : -0.902 (VIOLATED) Info: =================================================================== Info: One thing that stands out is that the data arrival path has a 2.939ns "clock network delay" while the data required path only has 0.241ns "clock network delay".
