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Altera_Forum's avatar
Altera_Forum
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17 years ago

Setting up SDC for input I/O?

Hi, I'm having I/O setup violations on input pins. The clock is driven by the FPGA, goes to an external FIFO that clocks out data to the FPGA inputs. The Tco of the external FIFO is max 7.7ns, ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

If you are doing a source synchronous bus, i.e using your clock60 as the clock that latches your data in to your external fifo then you probably want to use the -reference_pin command in your output delay. The reference pin is the name of the actual output port that your clock goes out on. The required timing is then calculated with respect to this latch edge then.

example

set_output_delay -clock { clock_that_clocks_out_your_data } -reference_pin [get_ports {your_clock60}] -min -4 [get_ports.......