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Altera_Forum
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17 years ago

Setting up SDC for input I/O?

Hi, I'm having I/O setup violations on input pins. The clock is driven by the FPGA, goes to an external FIFO that clocks out data to the FPGA inputs. The Tco of the external FIFO is max 7.7ns, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

That clock network delay probably isn't what you think it is. Use "-detail full_path" instead of "-detail path_only" for report_timing to see what is in the clock path.