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Altera_Forum
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17 years ago

Setting up SDC for input I/O?

Hi, I'm having I/O setup violations on input pins. The clock is driven by the FPGA, goes to an external FIFO that clocks out data to the FPGA inputs. The Tco of the external FIFO is max 7.7ns, ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

It is preferred to use a generated clock on the output device pin driving the clock instead of using -reference_pin. The generated clock is the more standard way to do it. However, both methods give exactly the same results if done correctly.