--- Quote Start ---
What i don't understand is why the zero time is not counted from the external CLK_OUT_60 pin which is what i intended to use as clock in the SDC. I must get something conceptually wrong since i would assume t=0 should be the CLK_OUT_60 element. In fact, if i specify the 60 MHz PLL clock as reference the timing violation goes away - i'm however not sure this approach is correct (neighter of the clock options appear correct, really).
--- Quote End ---
The "zero time" is arbitrary. In some cases neither launch nor latch edges will be at time zero. All that matters is the difference in time between launch and latch, and it is almost certain that TimeQuest is doing that correctly (except for cases that need multicycles to adjust the choice of launch or latch edge).
The generated clock on the output device pin driving the output clock or the equivalent reference pin must be traced back to its base clock, CLK_IN_48 in this case, so that TimeQuest can relate the timing on CLK_OUT_60 to the timing on the destination register in the FIFO. The destination register also has a clock ultimately based on CLK_IN_48, the base clock of the PLL.
You should not use an internal point in the clock network, PLL or otherwise, as the -clock argument for set_input_delay or set_output_delay or for the -reference_pin argument.
Honored Contributor
