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Altera_Forum's avatar
Altera_Forum
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14 years ago

Regarding Interconnect delay reduction in a design.

Dear sir,

This is manjunath, I am new to altera tool. My design is facing a problem of IC dealys ( Interconnected delays). I am not able to achieve max frequency of 250Mhz. In some critical paths the tool has routed too long path, which causing a huge IC delay.

Device used:EP4SGX530KH40C2

Quartus version: Q11.00

Example:

A lab cell at LABCELL_X124_Y98_N32 is driving a far placed DSP block DSPMULT_X99_Y82_N0. Due to this which is contributing IC delay of 1.417ns.

So Labcell is at (124,98) co-ordinate and DSPMULT is ar (99,82) co-ordinate.

Can you tell me how to reduce the IC delay. Is there any command to control the IC delay.

Thanks and Regards,

Manju.P

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Adding extra pipeline registers at the output of a module (or at the input of the receiving module) allows the fitter to put this extra register halfway effectively reducing IC-delays at the expense of an extra clock latency.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Dear sir,

    Thanks for replay,

    Actually the input to the module is also registered. Problem is after doing some computation, I will be registering it and then feed this registered data to a multiplication operation.

    In picture:

    ---- REG ------------COMBO-------------------REG------------------COMBO---

    -->reg_input-->combinatorial_logic -->reg_comb_logic_op--> multiplier->

    -----------------> My module logic starts

    So after computation of combinatorial_logic, I will be registering(reg_comb_logic_op). But actually registering is happening in the DSPMULTI block and then it is used by multiplier. This register moving from the normal logic location (124,98) to DSPMULTI location (99,82) is causing a huge interconnect delay (1.417ns).

    I hope you have understand the problem.

    Thank you,

    Manju.P
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Then try adding one more register in the chain:

    Reg1 --> Combo -->Reg2 --> Reg3 --> Combo --> ... Reg4

    The fitter will optimize the path between Reg1 and Reg2 to meet timing, it will optimize the timing from Reg3 to Reg4. The path between Reg2 and Reg3 should be easy to meet timing. But if this is not the case, e.g. if the destination is too far away from the source, adding yet another extra register between Reg2 and Reg3 will give the fitter even more headroom to meet timing.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Dear sir,

    Thanks for quick replay.

    But the problem is with the design is so tight that adding one more reg may screw up the functionality. Is there any command or constraints which will make sure that tool will always select the nearest available DSP block. So we can avoid IC delay. If there is no option then i have to redesign that part and also verify the design. One thing the design is for a video processing application, so the verification will take huge time. please suggest me some other way to fix the problem.

    Thank you,

    Manju.P
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It is very difficult to comment on your actual design, but to my idea it should always be possible to add pipeline registers, because even if can shift the routing to favour the 'problematic' connection, you may well end up with another timing violation in a different part of the design.

    I have no idea how to influence the routing, other than pipelining, but certainly the 'real' Altera gurus will jump in to help you out on that.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You can always use Logic Lock to force some parts of your design to be in a specific part of the FPGA, but it usually creates more timing problems than it solves. If you have constrained your design properly and specified all the clocks, the fitter usually finds an almost optimal solution, and trying to put your DSP block closer to the register might just create other worse timing problems in another part of the design.

    First you should have a look at the timing advisor (Tools menu I think). It will have a look at your project settings and suggest a few changes that can increase the fmax, if possible. If this isn't enough then I agree that you should add a pipeline level. It won't use that much resources, but will add one cycle latency in the signal processing and you may need to do other adaptations on your design to compensate for that.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Dear sir,

    Thanks for replay.

    The problem is the design has to work in different FPGA (xilinx and ALTERA, ASIC also in future). Now if i change by inserting a REG, it will not be generic design. It force us to have a different design version for different FPGA, Our aim is to make the design as generic one. Please suggest me with any switches or any constraints to achieve the goal.

    Thanks and Regards,

    Manju.P
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    IMHO adding the REG for he Altera design won't hurt the Xilinx nor the ASIC design later, just leave it in for every target.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Dear sir,

    Thank you.

    Ya agree with you. Consider in the case of ASIC, we will be increasing the REG count due to altera's routing technique. Here the problem is with area also, which should be min. If all the options are closed then, we have to go for REGISTERING. But still I believe there is some command is there to get solve this problem.

    Thanks and Regards,

    Manju.P