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Altera_Forum
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14 years ago

Regarding Interconnect delay reduction in a design.

Dear sir, This is manjunath, I am new to altera tool. My design is facing a problem of IC dealys ( Interconnected delays). I am not able to achieve max frequency of 250Mhz. In some critical p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

It is very difficult to comment on your actual design, but to my idea it should always be possible to add pipeline registers, because even if can shift the routing to favour the 'problematic' connection, you may well end up with another timing violation in a different part of the design.

I have no idea how to influence the routing, other than pipelining, but certainly the 'real' Altera gurus will jump in to help you out on that.