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Altera_Forum
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14 years ago

Regarding Interconnect delay reduction in a design.

Dear sir, This is manjunath, I am new to altera tool. My design is facing a problem of IC dealys ( Interconnected delays). I am not able to achieve max frequency of 250Mhz. In some critical p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

IMHO adding the REG for he Altera design won't hurt the Xilinx nor the ASIC design later, just leave it in for every target.