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Altera_Forum
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14 years ago

Regarding Interconnect delay reduction in a design.

Dear sir, This is manjunath, I am new to altera tool. My design is facing a problem of IC dealys ( Interconnected delays). I am not able to achieve max frequency of 250Mhz. In some critical p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Dear sir,

Thank you.

Ya agree with you. Consider in the case of ASIC, we will be increasing the REG count due to altera's routing technique. Here the problem is with area also, which should be min. If all the options are closed then, we have to go for REGISTERING. But still I believe there is some command is there to get solve this problem.

Thanks and Regards,

Manju.P