Regarding Interconnect delay reduction in a design.

Dear sir,

Thanks for quick replay.

But the problem is with the design is so tight that adding one more reg may screw up the functionality. Is there any command or constraints which will make sure that tool will always select the nearest available DSP block. So we can avoid IC delay. If there is no option then i have to redesign that part and also verify the design. One thing the design is for a video processing application, so the verification will take huge time. please suggest me some other way to fix the problem.

Thank you,

Manju.P