Regarding Interconnect delay reduction in a design.

You can always use Logic Lock to force some parts of your design to be in a specific part of the FPGA, but it usually creates more timing problems than it solves. If you have constrained your design properly and specified all the clocks, the fitter usually finds an almost optimal solution, and trying to put your DSP block closer to the register might just create other worse timing problems in another part of the design.

First you should have a look at the timing advisor (Tools menu I think). It will have a look at your project settings and suggest a few changes that can increase the fmax, if possible. If this isn't enough then I agree that you should add a pipeline level. It won't use that much resources, but will add one cycle latency in the signal processing and you may need to do other adaptations on your design to compensate for that.