Regarding Interconnect delay reduction in a design.

Dear sir,

Thanks for replay.

The problem is the design has to work in different FPGA (xilinx and ALTERA, ASIC also in future). Now if i change by inserting a REG, it will not be generic design. It force us to have a different design version for different FPGA, Our aim is to make the design as generic one. Please suggest me with any switches or any constraints to achieve the goal.

Thanks and Regards,

Manju.P