Regarding Interconnect delay reduction in a design.

Dear sir,

Thanks for replay,

Actually the input to the module is also registered. Problem is after doing some computation, I will be registering it and then feed this registered data to a multiplication operation.

In picture:

---- REG ------------COMBO-------------------REG------------------COMBO---

-->reg_input-->combinatorial_logic -->reg_comb_logic_op--> multiplier->

-----------------> My module logic starts

So after computation of combinatorial_logic, I will be registering(reg_comb_logic_op). But actually registering is happening in the DSPMULTI block and then it is used by multiplier. This register moving from the normal logic location (124,98) to DSPMULTI location (99,82) is causing a huge interconnect delay (1.417ns).

I hope you have understand the problem.

Thank you,

Manju.P