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AEsqu's avatar
AEsqu
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3 years ago

rapid recompile (signal tap logic analyzer flow) : out of memory

When I use the rapid recompile (signal tap logic analyzer flow, quartus std 21.1.0 Build 842) : out of memory (even with 64 GB or RAM).

Cyclone V FPGA, used at around 50%.

When I use the normal compile it works and uses about 10 GB or RAM (win 10).

Is there a rapid recompile bug?

Kind Regards,

Alex.

12 Replies

  • sstrell's avatar
    sstrell
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    How many nodes are you tapping and how many extra nodes are you allocating?

    • AEsqu's avatar
      AEsqu
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      Something like 20, no extra node, it just fail when putting out nodes for the first time.

      Same has no problem with normal compile.

  • ShengN_altera's avatar
    ShengN_altera
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    Hi Alex,


    Could you provide a sample design with the problem for testing?


    Thanks

    Best Regards

    Sheng


  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor

    Alex,


    May be you can delete db and incremental_db file (Standard/Lite) or qdb file (Pro) then recompile again. If the error still persist, may be you can try with larger RAM memory because place and route stage usually consumes more RAM compared to others.


    Thanks

    Best Regards

    Sheng


    • AEsqu's avatar
      AEsqu
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      Ok I will try to delete db / incremental_db then see if rapide recompile works.

      I noticed on the web that quartus has rapide compile issue with smart recompile enabled (set_global_assignment -name SMART_RECOMPILE ON) (which keeps data in incremental_db).

      It has maybe not been fixed yet?

    • AEsqu's avatar
      AEsqu
      Icon for Contributor rankContributor

      Hi,

      rapid recompile is not available when deleting the incremental_db/db directories, which makes sense.

      Turning off smart compilation does not help.

      Note that the normal compile flow uses about 10 GB.

      Looks like there is an issue with rapid recompile in certain RTL code situation.

      I had no issue with rapid recompile before I added a Synplify VQM,

      which fills much more the FPGA, but still. Maybe that rapid recompile has issue when .vqm is used.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor

    Hi Alex,


    May be you can check in task manager real time memory usage during rapid recompile. Is there any spike up consumes and exceeds the whole 64GB RAM?


    Thanks

    Best Regards

    Sheng


    • AEsqu's avatar
      AEsqu
      Icon for Contributor rankContributor

      Hi Sheng,

      Yes that was the case.

      I don't use rapid recompile but normal compile for now.

      See attached picture.

      Alex.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor

    Hi Alex


    Probably larger RAM memory is required for rapid recompile of Synplify VQM. Since there is no extra RAM available with you for now you may stick with normal compilation first.

    Let me know if the problem still exists even after expanding the RAM memory.

    Let me know also if any further updates or concerns.


    Thanks,

    Best Regards

    Sheng


  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor

    Since there are no further concerns for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.


  • AEsqu's avatar
    AEsqu
    Icon for Contributor rankContributor

    I received an email telling this:

    For your reference, we assigned this case ID number to your post: 05449850

    Does that mean that the issue will be corrected in the future?