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AEsqu's avatar
AEsqu
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3 years ago

rapid recompile (signal tap logic analyzer flow) : out of memory

When I use the rapid recompile (signal tap logic analyzer flow, quartus std 21.1.0 Build 842) : out of memory (even with 64 GB or RAM). Cyclone V FPGA, used at around 50%. When I use the normal c...
AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
3 years ago

I received an email telling this:

For your reference, we assigned this case ID number to your post: 05449850

Does that mean that the issue will be corrected in the future?