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AEsqu's avatar
AEsqu
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3 years ago

rapid recompile (signal tap logic analyzer flow) : out of memory

When I use the rapid recompile (signal tap logic analyzer flow, quartus std 21.1.0 Build 842) : out of memory (even with 64 GB or RAM). Cyclone V FPGA, used at around 50%. When I use the normal c...
sstrell's avatar
sstrell
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3 years ago

How many nodes are you tapping and how many extra nodes are you allocating?

AEsqu's avatar
AEsqu
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3 years ago

Something like 20, no extra node, it just fail when putting out nodes for the first time.

Same has no problem with normal compile.