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AEsqu's avatar
AEsqu
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3 years ago

rapid recompile (signal tap logic analyzer flow) : out of memory

When I use the rapid recompile (signal tap logic analyzer flow, quartus std 21.1.0 Build 842) : out of memory (even with 64 GB or RAM). Cyclone V FPGA, used at around 50%. When I use the normal c...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Alex,


May be you can delete db and incremental_db file (Standard/Lite) or qdb file (Pro) then recompile again. If the error still persist, may be you can try with larger RAM memory because place and route stage usually consumes more RAM compared to others.


Thanks

Best Regards

Sheng


AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
3 years ago

Ok I will try to delete db / incremental_db then see if rapide recompile works.

I noticed on the web that quartus has rapide compile issue with smart recompile enabled (set_global_assignment -name SMART_RECOMPILE ON) (which keeps data in incremental_db).

It has maybe not been fixed yet?