Error ID 18694: Still not resolved ???

Hi Frank,

thanks for your note. So it appears that we are on one line.

We did forward the question to our FAE engineer here, still waiting for the reply.

Meanwhile, I found a workaround:

- I need to transform the global clock from bank 3B into a local clock for bank 2J

- I define a bidirectional LVCMOS IO buffer on one of the bank 2J dedicated clock pins, otherwise unused

- I route the global clock to the input of that bidir buffer

- I retrieve the local bank 2J clock from the output of that bidir buffer

- of course I need OE=1, but Quartus forbids that as a static assignment (!!!!)

- so I create some Mickey-Mouse logic which toggles OE at some irrelevant point in time

- works beautifully, even at 1360 Mbit/sec, 136 MHz clock at factor 10 SERDES. I do not need that high rates, but testing it out just for fun.

Best regards

John

Hi John,
I wasn't aware of paragraph 5.6.6.3. The relation of 5.6.6.2.2 "The reference clock to the I/O PLL for the DPA or non-DPA LVDS receiver must come from the dedicated reference clock pin within the I/O bank" and 5.6.6.3 (you can manually promote reference clock from other I/O bank) is however not clearly stated. The manual can be read so that 5.6.6.3 doesn't apply for receiver SERDES.

I checked that manual promotion doesn't work for receiver PLL in Quartus Pro 22.4 and 24.3. You need to use an undocumented quartus.ini entry to enable reference clock promotion from other I/O bank.

I understand that Intel/Altera disabled reference clock promotion after Quartus 18 to "save" Cyclone 10 GX clock performance specification. However, as you stated, there are many medium speed SERDES designs that can well work with promoted reference clock.

Thus we are still waiting for an Altera application note undisclosing the respective Quartus.ini options. In the meantime, you may get on your FAE's nerves asking for the information.

Regards

Frank

Hi John,

May I know if you got any reply from the FAE engineer on this issue?

What is their feedback? If possible, I wanted to align with him.

Regards,

Aqid

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Hi, 

I didn't yet implement SERDES with Arria 10 but I assume that the behaviour is identical to Cyclone 10 GX as suggested by common IP doc. As for Arria 10 SERDES RX reference clock, I understand that fitter is enforcing this rule

5.6.6.2.2. Guideline: I/O PLL Reference Clock Source for DPA or Non-DPA Receiver

The reference clock to the I/O PLL for the DPA or non-DPA LVDS receiver must come from the dedicated reference clock pin within the I/O bank.

Note: This requirement is not applicable to LVDS transmitters.

Above reports seem to indicate that manual propagation according to 5.6.6.3 doesn't work in this case. Previous discussion in this thread addressed two possible solutions

• disabling fitter rule with an undocumented quartus.ini statement
• abusing a dedicated clock input as buffer by making it bidirectional and propagating clock to it.

I presume that reference clock restrictions have been introduced in later Quartus versions to guarantee SERDES performance at highest rates. Therefore I won't use discussed workarounds in this case but there should be no problem if you don't go to the limits.

If you do a hardware design or redesign aware of 5.6.6.2.2, you'll surely provide a dedicated reference clock per I/O bank.

Regards Frank

Hi,

for your info, error 18694 is still occurring with recent Quartus Prime Pro 26.1 

Regards Frank