Error(18694): The reference clock on PLL "u0|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll", 
which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. 
Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.