Forum Discussion
New ContributorError ID 18694: Still not resolved ???
- Hi,
hard to believe that you need to refer to weird workarounds like this...
Check your private message folder.
Regards,
Frank
Super ContributorHi Frank,
Could you post the full error id?
Possible provide the design for debug purpose?
Super ContributorHi Sheng,
thanks for your interest. What we see is expected behaviour according to above quoted 5.6.6.2.2. Guideline which requires refclock for SERDES RX being originated from a dedicated clock pin of same IO bank. Problem is that non-dedicated refclock source was possible in earlier Quartus versions and that it's strictly enforced by Quartus even for SERDES designs with rather uncritical clock speed. Previous statements suggested that this could be an unwanted effect, thus I verified that the behaviour is still present in latest Quartus Prime Pro 26.1. Error ID is 18694, as described in thread title. I append a test design with two SERDES instances located in bank 2F and 2G, both driven by bank 2F reference clock.
Regards Frank
- ShengN_altera
Hi Frank,
Please continue to use the INI to avoid the error. I had raised a new ticket to engineering team to fix this issue. Hopefully the problem will be fixed in future release.
EVANNew Member
Hi,
We are migrating an Arria 10 project from Quartus Prime Pro 17.1 to 24.1 and are currently blocked by Error (18694) related to the LVDS SERDES reference clock source.
The design uses a transceiver reference clock through HSSIREFCLKDIVIDER, which then drives external IOPLLs for LVDS TX banks. The same board and clock topology work correctly in Quartus 17.1, but Quartus 24.1 rejects the reference clock path during Fitter.
We have already tried using external PLLs, assigning the PLLs to the corresponding LVDS banks, as well as GLOBAL_CLOCK and REFCLK_FROM_CORE, but Error 18694 still remains.
We found references in the Altera Community indicating that there is an undocumented quartus.ini setting that can be used to bypass or relax this LVDS SERDES reference clock enforcement.
Could you please provide the corresponding quartus.ini setting or the recommended workaround for Quartus Prime Pro 24.1?
Device: Arria 10
Quartus version: Quartus Prime Pro 24.1
Error: 18694Thanks.
- EVAN
Hi,
We are migrating an Arria 10 project from Quartus Prime Pro 17.1 to 24.1 and are currently blocked by Error (18694) related to the LVDS SERDES reference clock source.
The design uses a transceiver reference clock through HSSIREFCLKDIVIDER, which then drives external IOPLLs for LVDS TX banks. The same board and clock topology work correctly in Quartus 17.1, but Quartus 24.1 rejects the reference clock path during Fitter.
We have already tried using external PLLs, assigning the PLLs to the corresponding LVDS banks, as well as GLOBAL_CLOCK and REFCLK_FROM_CORE, but Error 18694 still remains.
We found references in the Altera Community indicating that there is an undocumented quartus.ini setting that can be used to bypass or relax this LVDS SERDES reference clock enforcement.
Could you please provide the corresponding quartus.ini setting or the recommended workaround for Quartus Prime Pro 24.1?
Device: Arria 10
Quartus version: Quartus Prime Pro 24.1
Error: 18694Thanks.
