Quartus Prime Pro 21.3 - Timing Reproducibility in CI/CD

Great questions — this is a very common challenge in CI/CD-driven FPGA flows. Let me address each point directly.

Why you're seeing the variation

The behavior you're observing is expected and well-documented. The Fitter seed affects the initial placement configuration of the design, and any change in the initial conditions changes the Fitter results — each seed value results in a somewhat different fit. Quartus® Prime Pro Edition User Guide More importantly for your CI/CD scenario: any design change that directly or indirectly affects the Fitter has the same type of random effect as changing the seed value. This includes any change in source files, Compiler Settings, or Timing Analyzer Settings. The same effect can appear if you use a different computer processor type or different operating system, because different systems can change the way floating-point numbers are calculated in the Fitter. Quartus® Prime Pro Edition User Guide That explains the Linux vs. Windows divergence you're seeing.

On the magnitude of variation: on average, you can expect to see about ±5% variance in results across different seed values. There is no definitive seed value that guarantees the best results for every design — the varying results with seed value changes are design dependent. Change Fitter Placement Seeds

Best practices beyond a fixed seed and standardized environment

• Standardize the exact build environment rigorously. Almost any change to project settings, hardware, or software can impact results from one compilation to the next. This includes changes to .qsf, quartus2.ini, design files, and timing constraints (.sdc). Any setting that changes the number of processors during compilation can also impact compilation results, as can CPU architecture. Factors Affecting Compilation Results Lock down the OS, Quartus version (including build number), number of parallel threads, and CPU type in your CI runners.
• Add timing margin at the block level. Retaining approximately 10–20% timing margin at the block level can help achieve timing closure after integration of the blocks. Performance Planning General Guidelines A design sitting at –0.15 ns worst-case slack on some seeds has essentially no margin — the real fix is to improve QoR until timing passes consistently across seeds, not just to find the lucky seed.
• Run a seed sweep to characterize design robustness. Running a seed sweep (compiling your design with multiple seeds) determines whether the average result improved after an optimization change, and whether a setting that increases compilation time has benefits worth the increased time. The sweep also shows the amount of random variation to expect for your design. Quartus® Prime Pro Edition User Guide If your design fails on a significant fraction of seeds, the design itself needs more margin — no CI/CD trick will reliably hide that.
• After finalizing the design, lock the best seed. If your design is finalized, you can compile with different seeds to obtain one optimal result. However, if you subsequently make any changes to your design, you might need to perform a seed sweep again. Quartus® Prime Pro Edition User Guide In practice this means: run the seed sweep as part of your release process, commit the winning seed to the .qsf, and treat any subsequent RTL/constraint change as invalidating that choice.
• Be cautious with per-stage vs. full compilation flows. Compared to the full compilation flow, the per-stage compilation flow in Quartus Prime Pro Edition software may produce a slight Fmax difference, caused by random compiler variations equivalent to changing the Fitter Initial Placement Seed. If the design does not pass consistently across different seeds, add timing margin to absorb these variations. The Per-Stage Compilation Flow and the Full Compilation Flow Might Generate Slightly Different Fmax Results

Official Altera tools for automated seed sweeping

Yes — there are two complementary tools:

1. Design Space Explorer II (DSE II). DSE II processes a design using combinations of settings and constraints and reports the best combination for the design. You can also take advantage of DSE II parallelization to compile on multiple computers. An exploration point is a collection of Analysis & Synthesis, Fitter, and placement settings; a design exploration can also include different Fitter seeds. DSE II compiles the design using the settings for each exploration point, evaluates performance against an optimization goal you specify (timing, area, or power), and attempts multiple seeds to identify one meeting your requirements. DSE II can run different compilations on multiple computers in parallel to streamline timing closure. 1.1. Optimizing Settings with Design Space Explorer II You can invoke it from the command line via quartus_dse, which integrates well into CI scripts. Use DSE II included with the Quartus Prime software (by typing at a command prompt) to improve design performance by performing automated seed sweeping. Quartus® Prime Pro Edition User Guide
2. Exploration Dashboard. You can use the Exploration Dashboard (quartus_edw) in Quartus Prime Pro Edition software to aggregate and compare compilation results between multiple Quartus Prime projects or sets of compilation results. It allows you to easily coordinate and view the compilation and timing results from multiple projects running on separate instances of the Quartus Prime software. Aggregating and Comparing Compilation Results with Exploration Dashboard Use the Exploration Dashboard to quickly compare the aggregated compilation results from multiple projects or sets of results to determine the best implementation and impact of changes. Use cases include identifying all failing timing paths across all seeds after completing a seed sweep, and determining whether average fMAX improves after RTL optimization. Quartus® Prime Pro Edition User Guide Note: Exploration Dashboard is pre-production status in Quartus Prime Pro Edition v24.1, and supports analysis of compilation results generated with Quartus Prime Pro Edition software versions 21.1 through 24.1; other versions may function but are not verified. Aggregating and Comparing Compilation Results with Exploration Dashboard

Specifying the seed

To set the seed in your .qsf (which is easy to parameterize in CI): set_global_assignment -name SEED Quartus® Prime Pro Edition User Guide . The SEED setting is of type Integer and can be used in projects targeting any Intel FPGA device family. Quartus® Prime Pro Edition Settings File Reference Manual The default value is 1. Specify a starting value only if the Fitter is not meeting timing requirements by a small amount. Quartus® Prime Pro Edition Settings File Reference Manual

Bottom line recommendation for your CI/CD flow: Standardize the OS, CPU type, thread count, and exact Quartus build version across all runners. Use DSE II to run an automated seed sweep during the design stabilization phase, lock the best-performing seed into the .qsf, and re-sweep any time the RTL or constraints change materially. A design that passes timing only on select seeds is a design that needs more timing margin — target that as the root fix.

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