Error ID 18694: Still not resolved ???

Hi John,
I wasn't aware of paragraph 5.6.6.3. The relation of 5.6.6.2.2 "The reference clock to the I/O PLL for the DPA or non-DPA LVDS receiver must come from the dedicated reference clock pin within the I/O bank" and 5.6.6.3 (you can manually promote reference clock from other I/O bank) is however not clearly stated. The manual can be read so that 5.6.6.3 doesn't apply for receiver SERDES.

I checked that manual promotion doesn't work for receiver PLL in Quartus Pro 22.4 and 24.3. You need to use an undocumented quartus.ini entry to enable reference clock promotion from other I/O bank.

I understand that Intel/Altera disabled reference clock promotion after Quartus 18 to "save" Cyclone 10 GX clock performance specification. However, as you stated, there are many medium speed SERDES designs that can well work with promoted reference clock.

Thus we are still waiting for an Altera application note undisclosing the respective Quartus.ini options. In the meantime, you may get on your FAE's nerves asking for the information.

Regards

Frank