Error ID 18694: Still not resolved ???

Hi, 

I didn't yet implement SERDES with Arria 10 but I assume that the behaviour is identical to Cyclone 10 GX as suggested by common IP doc. As for Arria 10 SERDES RX reference clock, I understand that fitter is enforcing this rule

5.6.6.2.2. Guideline: I/O PLL Reference Clock Source for DPA or Non-DPA Receiver

The reference clock to the I/O PLL for the DPA or non-DPA LVDS receiver must come from the dedicated reference clock pin within the I/O bank.

Note: This requirement is not applicable to LVDS transmitters.

Above reports seem to indicate that manual propagation according to 5.6.6.3 doesn't work in this case. Previous discussion in this thread addressed two possible solutions

• disabling fitter rule with an undocumented quartus.ini statement
• abusing a dedicated clock input as buffer by making it bidirectional and propagating clock to it.

I presume that reference clock restrictions have been introduced in later Quartus versions to guarantee SERDES performance at highest rates. Therefore I won't use discussed workarounds in this case but there should be no problem if you don't go to the limits.

If you do a hardware design or redesign aware of 5.6.6.2.2, you'll surely provide a dedicated reference clock per I/O bank.

Regards Frank