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JohnGermany's avatar
JohnGermany
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Error ID 18694: Still not resolved ???

I have a LVDS SERDES TX IP in bank 2J of a Cyclone 10 GX device. I have a shared clock input pin in bank 3B. The current Cyclone 10 GX Core Fabric and IO manual, section 5.6.6.3, states that this c...
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  • FvM's avatar
    FvM
    1 year ago
    Hi,
    hard to believe that you need to refer to weird workarounds like this...

    Check your private message folder.

    Regards,
    Frank
Valyd16's avatar
Valyd16
Icon for New Contributor rankNew Contributor
4 months ago

Hi Frank, 

Thank you for your kind response.


100% If I do a new PCB design I will use the designated Bank I/O, but I already have a board unfortunately.

I am not sure exactly in which quartus.ini I should add? (I see there are multiple places and there is a quartus2.ini - I am not sure is that one).
It happens maybe that you maybe give me more details, and I could save much more time?


Best,
Val

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
4 months ago

Hi Val,

I don't feel legitimated to disclose undocumented quartus.ini statements in the forum.  Check your private messages.

Regards Frank