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AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
3 years ago

rapid recompile (signal tap logic analyzer flow) : out of memory

When I use the rapid recompile (signal tap logic analyzer flow, quartus std 21.1.0 Build 842) : out of memory (even with 64 GB or RAM). Cyclone V FPGA, used at around 50%. When I use the normal c...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Alex


Probably larger RAM memory is required for rapid recompile of Synplify VQM. Since there is no extra RAM available with you for now you may stick with normal compilation first.

Let me know if the problem still exists even after expanding the RAM memory.

Let me know also if any further updates or concerns.


Thanks,

Best Regards

Sheng